1. Field of the Invention
The present invention relates to semiconductor fabrication methods. More precisely, the present invention relates to a control system used in semiconductor fabrication for controlling feature critical dimensions.
2. Description of the Related Art
Two aspects of feature sizes are controlled in a lithographic and etch process. The first aspect is a critical dimension, the absolute size of a feature, including linewidth, spacing or contact dimensions. The second aspect is the variation in feature size across the wafer surface as measured by steps of a wafer stepper. Linewidth and spacing measurements are regularly performed to determine the actual sizes of critical dimensions at each masking level of a process.
Another aspect of linewidth control is that correct feature sizes are to be maintained across an entire wafer and also maintained from wafer to wafer. As a feature size is reduced, the tolerable error on feature size control is also reduced. When an exposure is performed by a wafer stepper, the feature size is controlled across every exposure field and field-to-field variations are to be held within specified limits.
Linewidth control is affected by many factors including fabrication tools and equipment, process recipes, and raw materials. Critical dimensions are analyzed by measuring fabricated test structures with nominal feature sizes at many positions of a wafer. The measurement results are then plotted as a function of location to determine critical dimension variation.
Linewidth control and control of critical dimensions is largely determined by specific characteristics of the steps of photoresist processing. Photoresist processing typically includes steps of substrate cleaning, dehydration baking and priming, spin coating, soft-baking or pre-baking, exposure, post-exposure treatment, a photoresist develop step, inspection following development, plasma de-scumming, post-baking, etching, deep ultraviolet hardening of photoresist, and stripping of the photoresist. Many of these steps are very important for determining linewidth control and control of critical dimensions. For example, dehydration baking and priming assures adhesion of the photoresist during processing. Poor adhesion can cause a loss of linewidth control including the entire loss of pattern elements in extreme cases.
The coating process including resist formulation, spinner type, wafer size, spin parameters, and ambient temperature during deposition determine the thickness variation across a wafer which, in turn, influences the critical dimensions across the wafer. Contamination with airborne particles and air bubbles can occur during the coating step. The soft-baking step can lead to wafer-to-wafer variations in critical dimensions since, for example, solvent vapors can coat infrared soft-baking lamps changing the energy output.
Exposure of the photoresist is a critical step in the resist processing procedure for several reasons. First, exposure is a step in which wafers are processed individually, leading to possible wafer-to-wafer variations in exposure. Second, the results of the exposure are highly dependent on photoresist thickness so that differences in coating thickness arising in the photoresist coating step are amplified during exposure.
Critical dimensions are conventionally tested by randomly sampling one wafer or a few wafers of a lot or multiple lots of processed wafers on post-develop inspection. If a sampled wafer is found to have critical dimensions that are outside specifications, another sample from the lots of processed wafers may be tested. If the subsequent test results in critical dimensions outside specified values, many wafers may be remeasured. If the critical dimensions are consistently outside the specification limits, the lot or entire group of lots are stripped of photoresist and reprocessed through the photolithography process.
The critical dimensions of polysilicon gates affect many operating parameters of integrated circuits, but fundamentally the greatest considerations of critical dimensions is speed performance and power consumption of a circuit. The smaller this critical dimension, the faster the operation of the transistor and the integrated circuit as a whole. Too small a polysilicon gate critical dimension, however, results in unacceptably high power consumption and parasitic currents in the transistor. An optimal operating point for this critical dimension is therefore defined by these countervailing effects. Thus, the narrower the distribution of critical dimension values centered about the optimal critical dimension in a lot of wafers, the more high speed, functional circuits are produced. Unfortunately, the critical dimensions resulting from conventional manufacturing methods are rarely optimum, resulting in reduced yield of high performance circuits. Furthermore, the conventional process is very wasteful when process conditions are substandard.
What is needed is a technique for reducing polysilicon gate linewidth variability and controlling the process at, or very near, the optimal linewidth value. What is further needed is a technique for reducing lot average critical dimensions in a polysilicon gate etch process without negatively impacting other parameters such as uniformity and line shape.